AT17C128 Overview
Description
The AT17C65/128/256 and AT17LV65/128/256 (low-density AT17 Series) FPGA configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The low-density AT17 Series is packaged in the 8-lead LAP, the 8-lead PDIP, the 8-lead SOIC and the popular 20-lead PLCC.
Key Features
- In-System Programmable (ISP) via 2-wire Bus
- Simple Interface to SRAM FPGAs
- Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
- Low-power CMOS EEPROM Process
- Programmable Reset Polarity
- Emulation of Atmel’s AT24CXXX Serial EEPROMs
- Available in 3.3V ± 10% LV and 5V ± 5% C Versions
- Low-power Standby Mode
